Qualcomm
ASICS Design Verification Engineer-Senior
$122K–$183K
San Diego, California · On-site · Senior · Full-time · Posted Sep 17, 2026
- Experience
- 2+ years with a bachelor’s degree; 1+ year with a master’s degree; no years specified with a PhD. Preferred qualifications mention 6+ years in several areas.
- Education
- Bachelor’s, master’s, or PhD in Science, Engineering, or a related field; preferred master’s in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field.
About the job
Performs pre-silicon verification of digital power IP, from test planning and testbench development through coverage, formal checks, power-aware verification, and automation.
What you'll do
- Develop verification plans, SystemVerilog-UVM testbenches, coverage, and assertion models for digital power IP.
- Perform formal verification and deploy power-aware UPF verification flows and methodology.
- Develop automation to improve verification efficiency.
What they ask for
- Bachelor’s degree in Science, Engineering, or a related field plus 2+ years of relevant work experience; or a master’s degree in those fields plus 1+ year; or a PhD in those fields.
- 2+ years of experience with ASIC design and verification tools, techniques, and methodology.
Nice to have
- Experience with AMBA Bus protocol (AXI/AHB/APB etc).
- Knowledge or experience with Assertion Based Formal Verification.
Pay
$121,800.00 - $182,600.00 USD base salary
Tools
SystemVerilog-UVM, UPF, SystemVerilog, Verilog, VHDL, C, C++, Perl or python
Model-written summary · the original posting is authoritative