Qualcomm
ASICS Design Verification Engineer-Senior
$122K–$183K
San Diego, California · On-site · Senior · Full-time · Posted Oct 19, 2026
- Experience
- Bachelor’s: 2+ years; master’s: 1+ year; PhD: no experience stated. Separately, the qualifications section lists 2+ years; preferred qualifications list 6+ years in several areas.
- Education
- Bachelor's degree in Science, Engineering, or related field; master's degree in Science, Engineering, or related field; or PhD in Science, Engineering, or related field.
About the job
Develops and verifies digital power IP across the pre-silicon lifecycle, including test planning, testbench and coverage development, formal verification, power-aware verification, and automation.
What you'll do
- Create pre-silicon test plans, testbenches, coverage, and assertion models for digital power IP.
- Perform formal verification and learn and deploy power-aware UPF verification flows and methodologies.
- Develop automation to improve verification efficiency.
What they ask for
- Bachelor’s degree in Science, Engineering, or a related field and 2+ years of relevant work experience; or a master’s degree in those fields and 1+ year; or a PhD in those fields.
- 2+ years of experience with ASIC design and verification tools, techniques, and methodology.
Nice to have
- Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory).
- Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory).
Pay
$121,800.00 - $182,600.00 USD base salary
Tools
SystemVerilog-UVM, UPF, SystemVerilog, Verilog, VHDL, C, C++, Perl
Model-written summary · the original posting is authoritative