Qualcomm
ASICS Design Verification Engineer-Senior to Staff
$122K–$183K
San Diego, California · On-site · Staff · Full-time · Posted Oct 23, 2026
- Experience
- Minimum: 2+ years with a bachelor's degree, 1+ year with a master's degree, or no minimum years stated with a PhD. Preferred qualifications include 6+ years in several ASIC verification, digital design, architecture, programming, testbench, methodology, and scripting areas.
- Education
- Bachelor's degree in Science, Engineering, or related field; alternatively, a master's degree in those fields or a PhD in those fields. The qualifications section also lists a bachelor's degree in Engineering, Science, or a closely related field.
About the job
Verifies digital power IP across the pre-silicon lifecycle, including test planning, testbench and coverage development, formal verification, power-aware verification, and automation.
What you'll do
- Develop pre-silicon test plans, testbenches, coverage, and assertions for digital power IP.
- Deploy power-aware UPF verification flows and formal property checking.
- Develop automation to improve verification efficiency.
What they ask for
- Bachelor's degree in Science, Engineering, or a related field plus 2+ years of relevant experience; or a master's degree plus 1+ year; or a PhD.
- 2+ years of experience with ASIC design and verification tools, techniques, and methodology.
Nice to have
- Experience with AMBA Bus protocols (AXI/AHB/APB, etc.) (desirable, not mandatory).
- Knowledge or experience with Assertion Based Formal Verification (desirable, not mandatory).
Pay
$121,800.00 - $182,600.00 USD base salary
Tools
SystemVerilog-UVM, UPF, SystemVerilog, Verilog, VHDL, C, C++, Perl
Model-written summary · the original posting is authoritative