Qualcomm
CAD and PPA Methodology Engineer
$170K–$254K
San Diego, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- Minimum: 4+ years with a bachelor's degree, 3+ years with a master's degree, or 2+ years with a PhD. Preferred: 5–7 years developing methodologies for PPA improvement.
- Education
- Bachelor's, master's, or PhD in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
About the job
Develops CAD flows, methodologies, and algorithms to improve power, performance, and area in GPU cores, collaborating with design and implementation teams.
What you'll do
- Develop and improve PPA flows, methodologies, and algorithms for GPU cores.
- Work with design, technology, power, implementation, sign-off, and post-silicon teams to drive PPA improvements.
- Support ASIC design activities from RTL to GDS, including synthesis, timing analysis, formal verification, physical design, and ECOs.
What they ask for
- Bachelor's degree in a related field and 4+ years of relevant work experience; or master's degree and 3+ years; or PhD and 2+ years.
- Basic understanding of digital design and RTL development.
- Experience with PPA improvement methodology development (listed as a preferred qualification: at least 5–7 years).
- Hands-on experience with EDA tools, and scripting experience in at least one listed language (both listed as preferred qualifications).
Nice to have
- GPU core implementation from RTL to GDSII; semi-custom design flow and methodology development.
- Verilog/System-Verilog, physically aware RTL synthesis, design constraint management, formal verification, clock tree optimization, and ECO methods.
Pay
$169,500.00 - $254,300.00 USD base salary
Tools
Verilog, System-Verilog, Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower, PrimeTime, UNIX shell, Python
Model-written summary · the original posting is authoritative