Drimva

Qualcomm

CPU-Core RTL Director

$228K–$343K

Austin, Texas +1 · On-site · Director · Full-time · Posted Sep 18, 2026

Location
Austin, Texas
Santa Clara, CA
Experience
12+ years in CPU RTL design, microarchitecture, or related semiconductor development; 3+ years leading teams or large technical projects. Minimum qualifications also state 8+ years with a bachelor's, 7+ with a master's, or 6+ with a PhD.
Education
Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field; MS or PhD preferred.

About the job

Leads CPU RTL engineering teams and delivers high-performance, low-power CPU cores from architecture and RTL development through silicon bring-up and product delivery.

What you'll do

  • Direct CPU microarchitecture and RTL implementation, guiding design quality, timing closure, power optimization, and technical tradeoffs.
  • Own project execution, milestones, risk mitigation, and cross-functional coordination through tapeout and post-silicon support.
  • Recruit, mentor, and develop engineers while shaping team priorities and contributing to CPU roadmap planning.

What they ask for

  • Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
  • 12+ years of experience in CPU RTL design, microarchitecture, or related semiconductor development.
  • 3+ years of experience leading engineering teams or large technical projects.
  • Strong understanding of modern high-performance CPU architecture and microarchitecture, with experience delivering complex RTL designs into production silicon.

Nice to have

  • MS or PhD in a related discipline; deep expertise in one or more CPU design domains.
  • Experience with SystemVerilog, timing closure, physical design, power optimization, cross-functional execution, or AI-assisted design workflows.

Pay

$228,400.00 - $342,600.00 USD base salary

Tools

SystemVerilog

AI focus

Preferred experience includes driving AI-assisted design workflows and engineering productivity improvements.

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 5, 2026 (UTC)