Qualcomm
CPU DFT Engineer
$148K–$222K
Santa Clara, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- 5+ years of practical experience; also states 3+ years in test or DFT. Minimum-qualification alternatives: bachelor’s plus 2+ years of related work experience, master’s plus 1+ year, or PhD.
- Education
- BA/BS in Electrical/Computer Engineering; minimum-qualification alternatives include a relevant bachelor’s or master’s degree, or PhD.
About the job
Verifies and implements DFT and design-for-debug architecture, implementation, and test plans for digital and mixed-signal VLSI designs.
What you'll do
- Create test vectors or oversee their creation, and validate DFT requirements.
- Work with designers to improve test coverage, debug observability, and flexibility; verify post-PD designs meet DFT requirements.
- Coordinate with test personnel and run tests when needed.
What they ask for
- Bachelor’s degree in Electrical/Computer Engineering with 5+ years of practical experience; the posting also lists alternatives of a relevant bachelor’s degree plus 2+ years of related work experience, a relevant master’s plus 1+ year, or a relevant PhD.
- Strong digital ASIC design fundamentals and experience with Verilog or VHDL.
- Experience with ASIC test, DFT, and debug; 3+ years of practical experience with test or DFT.
- Experience with Mentor Tessent, SOC-level verification on large designs, and TCL, Perl/Python, and Shell scripting.
Nice to have
- Hands-on expertise with commercial test-generation tools for large complex designs.
- Knowledge of JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, MBIST, and LBIST; experience running test-compression software.
Pay
$147,900.00 - $221,900.00 USD base salary
Tools
Verilog, VHDL, Mentor Tessent, TCL, Perl/Python, Shell, JTAG, ATPG
Model-written summary · the original posting is authoritative