Qualcomm
CPU Physical Design Timing Engineer (Austin, TX)
$130K–$194K
Austin, Texas · On-site · Full-time · Posted Sep 17, 2026
- Experience
- Bachelor’s: 2+ years of related work experience; master’s: 1+ year; PhD: no work-experience minimum stated.
- Education
- Bachelor’s, master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Drive timing closure and signoff for Oryon CPU cores, developing timing constraints, STA flows, and automation to meet performance, power, and area goals.
What you'll do
- Set up, converge, review, and sign off STA for multi-mode, multi-voltage CPU designs; analyze and debug timing across PVT conditions.
- Develop automation scripts and CPU STA signoff flows; optimize STA and correlate Spice results with STA.
- Investigate timing miscorrelation, evaluate timing methodologies and tools, and collaborate with CPU design and implementation teams.
What they ask for
- Excellent automation skills using TCL/Perl/Python.
- Ability to develop automation scripts from a specification for CPU STA signoff flow or methodology.
- Bachelor’s degree in a related field and 2+ years of relevant work experience; or master’s degree and 1+ year; or PhD in a related field.
- Familiarity with digital implementation flow from RTL to GDS using ICC, Innovus, and PT/Tempus.
Nice to have
- Framework, tool, or utility development experience.
- Expertise in STA timing analysis, timing constraints, AOCV/POCV, CTS, crosstalk, signal integrity, and ASIC back-end flows.
Pay
$129,500.00 - $194,300.00 USD base salary
Tools
TCL, Perl, Python, PT/Tempus, Prime-time, Spice, ICC, Innovus
Model-written summary · the original posting is authoritative