Drimva

Qualcomm

CPU RTL Power Engineer

$155K–$233K

Austin, Texas +1 · On-site · Full-time · Posted Sep 17, 2026

Location
Austin, Texas
Santa Clara, CA
Experience
3–8 years of CPU RTL power modeling and estimation experience. Minimum qualifications also state alternatives: bachelor's degree and 4+ years, master's degree and 3+ years, or PhD and 2+ years of related work experience.
Education
BS degree in Electrical or Computer Engineering. Minimum qualifications also list a bachelor's, master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the job

Models and analyzes CPU RTL power, then optimizes high-performance CPU designs for power targets and efficiency.

What you'll do

  • Estimate and optimize RTL power for CPU modules, collaborating with architecture, RTL, verification, and physical design teams.
  • Create CPU power models, establish early power targets, correlate estimates with physical design, and analyze power/performance/area tradeoffs.
  • Build scripts to automate power analysis and develop algorithms for analyzing hardware throttling mechanisms within performance and power limits.

What they ask for

  • BS degree in Electrical or Computer Engineering with 3–8 years of CPU RTL power modeling and estimation experience.
  • Deep understanding of CPU or ASIC low-power design, including active and idle power optimization, RTL clock gating, power analysis, and battery-life projections.
  • Working knowledge of Verilog and/or VHDL and hands-on experience with low-power simulation tools such as PowerArtist and PTPX.
  • Knowledge of logic design principles and their power and timing implications.

Nice to have

  • MS degree in Computer or Electrical Engineering with at least 3 years of practical experience.
  • Experience using Perl or Python.

Pay

$155,400.00 - $233,200.00 USD base salary

Tools

Verilog, VHDL, PowerArtist, PTPX, Perl, Python

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 5, 2026 (UTC)