Qualcomm
CPU Server Floorplan and Integration Engineer
$148K–$222K
Santa Clara, California · On-site · Full-time · Posted Sep 22, 2026
- Experience
- Bachelor's: 2+ years of relevant work experience; master's: 1+ year; or PhD (no work-experience minimum stated).
- Education
- Bachelor's, master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
About the job
Designs, floorplans, integrates, and validates CPU physical designs to meet power, area, and performance goals for server products.
What you'll do
- Perform CPU physical design, including floorplanning, Bump/RDL planning, IP integration, power/ground generation, and pin assignment.
- Manage chip-level place and route, optimize area and block partitioning, and finalize the CPU database for construction and verification.
- Develop chip integration and analysis workflows and coordinate with internal and external teams on integration and IP requirements.
What they ask for
- Proficiency in synthesis, place and route, and signoff timing/power analysis.
- Experience with block-level implementation, full-chip floorplanning, and power grid planning.
- Knowledge of physical design, integration, and verification of large processor and SoC designs, including extraction, STA, and EMIR flows.
- Bachelor's, master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with the work-experience alternatives stated in the posting.
Nice to have
- Experience in deep submicron process technology nodes.
- Experience as a key technical lead driving physical design database development and delivery; understanding of industry-standard synthesis, place & route, and tapeout tools.
Pay
$147,900.00 - $221,900.00 USD base salary
Tools
synthesis, place and route, static timing analysis (STA), EMIR, Bump/RDL
Model-written summary · the original posting is authoritative