Qualcomm
CPU Server FV/CLP/STA engineer
$148K–$222K
Santa Clara, California · On-site · Full-time · Posted Sep 28, 2026
- Experience
- Bachelor's degree plus 2+ years of relevant work experience; or master's degree plus 1+ year; or PhD (no additional experience stated).
- Education
- Bachelor's, master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Develops and analyzes synthesis, formal verification, power checks, and static timing for complex CPU server designs, addressing timing, area, power, and congestion trade-offs.
What you'll do
- Perform multi-million-gate synthesis and physical synthesis; develop constraints for multi-clock timing analysis.
- Conduct formal verification, structural power checks, and pre-layout STA; debug issues and generate timing ECOs.
- Analyze design trade-offs and collaborate proactively with stakeholders.
What they ask for
- Working knowledge of physical synthesis tools such as DC, Genus, or Fusion Compiler.
- Experience developing constraints for multi-clock domains and hierarchical or flat timing analysis.
- Good working knowledge of multi-power-domain synthesis and structural power checks using CLP.
- Hands-on formal verification experience, strong debugging skills, and good knowledge of pre-layout STA and timing reports.
Nice to have
- Knowledge of hierarchical STA with Hyperscale.
- Exposure to TCL scripting for synthesis or STA.
Pay
$147,900.00 - $221,900.00 USD (base salary)
Tools
DC, Genus, Fusion Compiler, CLP, TCL, Hyperscale
Model-written summary · the original posting is authoritative