Qualcomm
CPU Server Physical Design Clock Engineer
$148K–$222K
Santa Clara, California · On-site · Full-time · Posted Sep 22, 2026
- Experience
- Bachelor’s degree: 2+ years of relevant work experience; OR master’s degree: 1+ year; OR PhD: no experience specified. Preferred qualifications also state 4+ years of practical experience.
- Education
- Bachelor’s, master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Develop and validate clock generation and distribution solutions for next-generation CPUs, optimizing clock skew and power with design and CAD teams.
What you'll do
- Perform jitter analysis and measurements, and provide physical design teams with feedback on fixes.
- Implement and validate CPU clocking with design teams.
- Drive CPU clock generation and distribution methodology, coordinating clocking techniques to optimize skew and power.
What they ask for
- Experience constructing and analyzing low-skew, low-power clock generation and distribution.
- Experience with clock H-tree, mesh, spines, and CTS implementations.
- Understanding of device physics, RC delay, and electrical aspects.
- Proficiency in SPICE simulation and analysis for circuit design and verification.
Nice to have
- MS in Electrical Engineering; 4+ years of practical experience.
- Experience with deep submicron process technology nodes; proficiency in PLL specifications, clock skew estimation, and jitter measurements.
Pay
$147,900.00 - $221,900.00 USD base salary
Tools
SPICE, PLL, CTS
Model-written summary · the original posting is authoritative