Qualcomm
CPU Server Physical Design Clock Engineer
$155K–$233K
Austin, Texas · On-site · Full-time · Posted Sep 17, 2026
- Experience
- Bachelor's degree: 4+ years; master's degree: 3+ years; PhD: 2+ years of relevant work experience. Preferred qualifications also state 8+ years of practical experience.
- Education
- Bachelor's, master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Creates and validates clock generation and distribution solutions for next-generation CPUs, optimizing clock skew, power, and jitter.
What you'll do
- Implement and validate CPU clocking with design teams and drive CPU clock-generation and distribution methodology.
- Collaborate with CAD and block-level designers to optimize clocking techniques for skew and power.
- Analyze and measure jitter, then advise physical-design engineers on needed fixes.
What they ask for
- Experience constructing and analyzing low-skew, low-power clock generation and distribution.
- Experience with clock H-tree, mesh, spines, and CTS implementations.
- Understanding of device physics, RC delay, and electrical aspects.
- Proficiency in SPICE simulation and analysis for circuit design and verification.
Nice to have
- Skilled in chip physical design, standard-cell optimization, and clock construction; experience defining clock methodology.
- Deep-submicron process experience; PLL specifications, clock-skew estimation, and jitter measurements.
Pay
$155,400.00 - $233,200.00 USD base salary
Tools
SPICE, CTS, PLL
Model-written summary · the original posting is authoritative