Qualcomm
CPU Server Physical Design Timing Engineer
$176K–$263K
Santa Clara, California · On-site · Full-time · Posted Sep 22, 2026
- Experience
- Bachelor's: 4+ years; Master's: 3+ years; PhD: 2+ years of relevant work experience.
- Education
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
About the job
Drives static timing analysis, closure, signoff, and methodology development for Oryon CPU cores to meet power, area, and performance goals.
What you'll do
- Set up, analyze, debug, converge, review, and sign off timing for Oryon CPU designs across modes, voltage domains, and PVT conditions.
- Develop and optimize STA flows, correlate Spice and STA results, and investigate timing miscorrelation across design levels and modes.
- Build automation scripts and timing infrastructure, and collaborate with CPU design, implementation, and timing methodology teams.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant work experience; OR Master's degree in one of these fields or related field and 3+ years; OR PhD in one of these fields or related field and 2+ years.
- Strong experience in design automation using TCL/Perl/Python.
- Familiarity with digital implementation flow from RTL to GDS and tools including ICC, Innovous, and PT/Tempus.
Nice to have
- Expertise in STA timing analysis, AOCV/POCV, CTS, timing constraints, latch transparency, and 0-cycle and multi-cycle paths.
- Experience with Prime-time or Tempus, timing convergence at chip and hard-macro level, signal integrity, parasitic extraction, and ASIC back-end flows.
Pay
$175,600.00 - $263,400.00 USD base salary
Tools
PT/Tempus, Primetime, Spice, TCL, Perl, Python, ICC, Innovous
Model-written summary · the original posting is authoritative