Qualcomm
CPU SRAM Design & Layout Engineer
$148K–$222K
Santa Clara, California · On-site · Full-time · Posted Sep 9, 2026
- Experience
- The General Summary asks for 5+ years of relevant industry experience with a bachelor's degree, or 2+ years with a master's degree. The separate Minimum Qualifications section states a bachelor's degree and 2+ years of related work experience, or a master's degree and 1+ year, or a PhD.
- Education
- General Summary: Bachelor's degree in Electrical Engineering or related field, or Master's degree in Electrical Engineering. Minimum Qualifications: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
About the job
Designs and delivers high-performance custom SRAMs and register files, from circuit design and layout through verification, characterization, and model generation.
What you'll do
- Design and optimize SRAM and register-file circuits, schematics, floorplans, and custom layouts.
- Own memory implementation, physical verification, signoff, and timing, power, and electrical characterization.
- Collaborate with CAD and Physical Design teams on memory modeling, automation, and PPA challenges.
What they ask for
- Experience designing custom SRAM circuits and register files and implementing custom memory layouts.
- Experience with circuit simulation, Monte Carlo analysis, and static timing analysis.
- Knowledge of advanced semiconductor technologies, including FinFET and nanosheet process nodes, and deep sub-micron layout design.
- Experience with Cadence Virtuoso and Calibre LVS/DRC verification flows.
Nice to have
- Experience with memory logical models (Verilog), BIST, DFT, or memory automation flows.
- Proficiency with NanoTime, Ansys EMIR, ESP-CV, Liberate, or SKILL code.
Pay
$147,900.00 - $221,900.00 USD base salary
Tools
Cadence Virtuoso, Calibre LVS/DRC, Verilog, NanoTime, Ansys EMIR, ESP-CV, Liberate, SKILL
Model-written summary · the original posting is authoritative