Qualcomm
CPU STA CAD Engineer
$209K–$314K
Santa Clara, California +2 · On-site · Full-time · Posted Oct 2, 2026
- Location
- Santa Clara, California
Austin, Texas
San Diego, California - Experience
- 6+ years with a bachelor's degree, 5+ years with a master's degree, or 4+ years with a PhD in a related field.
- Education
- Bachelor's, master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Build and support static timing analysis and timing-closure tools and flows for custom CPUs, improving power, performance, and area.
What you'll do
- Maintain, support, and debug STA and timing-closure (ECO) flows; resolve project-specific issues.
- Work with CPU physical-design teams to provide methodology guidance and tools and flows support.
- Recommend methodology improvements and collaborate with EDA vendors on roadmaps and tool issues.
What they ask for
- Bachelor's degree in a related field and 6+ years of relevant work experience, or master's degree and 5+ years, or PhD and 4+ years.
- Experience with Static Timing Analysis (STA) on cutting-edge technology nodes.
- Programming/scripting skills, particularly Python and Tcl.
- Detailed understanding of STA concepts and their impact on margins and derates.
Nice to have
- Experience generating, optimizing, or automating timing ECO closure; Synthesis/PnR experience focused on PPA optimization.
- Experience applying AI techniques to EDA workflows; web, database, dashboards, or visualization experience is a plus.
Pay
$209,300.00 - $313,900.00 USD (pay range; salary component)
Tools
Python, Tcl, STA, LVF, CCS, SSI, NBTI, CI/CD
AI focus
Apply AI techniques to EDA workflows, including log analysis, root-cause investigation, metrics mining, knowledge retrieval, and automated generation of scripts, documentation, and test collateral.
Model-written summary · the original posting is authoritative