DDR Validation Lead, Staff (AI Accelerator Platform)

What you'll do

• Define and execute DDR validation across emulation, FPGA, and silicon, including bring-up, training, performance, reliability, power, and stress testing.
• Lead debug of memory controller, PHY, firmware, SI/PI, timing, and system-level issues; validate interactions with processors, accelerators, caches, NoC, and software.
• Build automation, regression, and debug analytics, and characterize memory performance with AI workloads.

What they ask for

• BS, MS, or PhD in EE, CE, CS, or a related field.
• 5+ years in DDR/memory subsystem validation or silicon bring-up.
• Strong understanding of LPDDR architectures, DDR controllers and PHYs, memory training, cache/coherency/NoC, and low-power memory features; strong post-silicon debug experience.
• Proficiency in C/C++ and low-level software development.

Nice to have

• Mobile SoC, AI compute, automotive, or server platform validation experience.
• Familiarity with SI/PI analysis, memory performance tuning, and thermal characterization; first-silicon bring-up or volume production qualification experience.

Pay

$145,600.00 - $218,400.00 USD base salary

Tools

LPDDR5X, LPDDR6, LPDDR4/5/5X/6, C/C++, DDR controllers, PHYs, FPGA, NoC

AI focus

Validates DDR memory subsystems on AI accelerator platforms and characterizes bandwidth, latency, QoS, memory pressure, and AI workloads.