Qualcomm
DDRSS Validation Engineer (RTL + Silicon Debug)
$146K–$218K
San Diego, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- 6–9 years in SoC validation, design verification, or post-silicon validation. Minimum qualifications also specify a bachelor's degree and 4+ years, a master's degree and 3+ years, or a PhD and 2+ years of relevant ASIC work experience.
- Education
- Bachelor's, master's, or PhD in Science, Engineering, or a related field.
About the job
Validates DDR and other SoC subsystems across RTL simulation, emulation, and silicon, developing C firmware and debugging issues through silicon bring-up.
What you'll do
- Drive end-to-end validation of DDR, memory controller, cache, and interconnect subsystems across simulation, emulation, and silicon.
- Develop and maintain C firmware for DDR initialization, frequency and power management, bring-up, and feature validation.
- Debug RTL, firmware, and silicon failures; build tools and automation to improve validation and failure triage.
What they ask for
- Strong debugging skills in Verilog/SystemVerilog simulation environments.
- Experience developing embedded firmware in C.
- Hands-on silicon bring-up, debug, and validation experience, including debugging across simulation, emulation, and silicon.
- Understanding of computer architecture, SoC subsystems, and memory systems such as DDR, cache, and interconnect.
Pay
$145,600.00 - $218,400.00 USD base salary
Tools
Verilog, SystemVerilog, C, RTL simulation, Emulation
Model-written summary · the original posting is authoritative