Qualcomm
Design Engineer (Low Power)
$190K–$285K
Santa Clara, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- 7+ years in ASIC Design; 2+ years in low-power work. Minimum qualification alternatives: bachelor's degree plus 6+ years, master's degree plus 5+ years, or PhD plus 4+ years in ASIC design, verification, validation, integration, or related work.
- Education
- Bachelor's, master's, or PhD in Science, Engineering, or related field.
About the job
Designs and delivers low-power SoC micro-architecture and ASIC implementations for WiFi technology, from specification through silicon bring-up and power correlation.
What you'll do
- Develop technical specifications and low-power micro-architecture/design from architectural and system requirements; own the design through ASIC development, including RTL, verification, synthesis, timing closure, emulation, and post-silicon bring-up.
- Work with verification teams on plans and debugging; perform silicon power measurements, silicon debug, and power correlation.
- Develop full-chip debug design using ARM IPs.
What they ask for
- 7+ years of working experience in ASIC Design; minimum qualifications also specify 6+ years with a bachelor's degree, 5+ years with a master's degree, or 4+ years with a PhD.
- 2+ years of experience in low-power micro-architecture, design, Power Intent/Implementation, power optimization, and power estimation.
- Experience in silicon bring-up and debug.
- Experience with SoC micro-architecture, multi-domain clocking, and AMBA bus protocols such as AHB and APB.
Nice to have
- ARM IP-based full-chip debug; AXI.
- PCIE/USB peripherals, CPU subsystem-based design, or low-power design from project start through volume production for at least one product cycle.
Pay
$190,200.00 - $285,400.00 (USD, base salary)
Tools
WiFi (802.11x), SoC, RTL, ARM IPs, AMBA, AHB, APB, AXI
Model-written summary · the original posting is authoritative