Qualcomm
Design Verification Engineer — Memory Subsystem
$160K–$239K
Santa Clara, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- The posting states 3–10 years of ASIC, SoC, IP, or subsystem design verification. Minimum qualifications specify a Bachelor’s degree and 4+ years, or a Master’s degree and 3+ years, or a PhD and 2+ years of ASIC-related experience.
- Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Minimum qualifications also list a PhD in Science, Engineering, or a related field.
About the job
Develops and executes verification for complex memory-subsystem designs, from verification planning and UVM testbench development through debugging and coverage closure.
What you'll do
- Develop verification strategies, test plans, UVM environments, tests, and assertions for RTL and memory-subsystem designs.
- Run simulations and regressions; debug failures, perform root-cause analysis, and collaborate with design and cross-functional teams.
- Drive functional, code, assertion, and coverage closure.
What they ask for
- Hands-on experience with Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
- Experience developing and debugging reusable UVM environments and components, and using constrained-random and coverage-driven verification.
- Experience with simulation-based verification, waveform analysis, regressions, and failure debugging; understanding of digital design fundamentals, including clock/reset and multi-clock-domain designs.
- Bachelor’s or Master’s degree in a related technical field; minimum qualifications also allow a PhD under the stated experience alternative.
Nice to have
- Experience with LPDDR, DDR, DDR PHY, HBM, custom memory interfaces, or JEDEC specifications.
- Experience with formal verification, UPF, standard interfaces, memory models, or memory-subsystem performance verification.
Pay
$159,600.00 - $239,400.00 USD base salary
Tools
Verilog, SystemVerilog, UVM, SystemVerilog Assertions, UPF, AXI, APB, DFI
Model-written summary · the original posting is authoritative