Qualcomm
DFT Engineering Director
$216K–$325K
San Diego, California · On-site · Director · Full-time · Posted Oct 30, 2026
- Experience
- 8+ years with a bachelor's degree, 7+ years with a master's degree, or 6+ years with a PhD in ASIC design, verification, validation, integration, or related work experience; preferred: 15+ years in advanced DFT/DFD implementation and verification.
- Education
- Bachelor's, master's, or PhD in Science, Engineering, or related field.
About the job
Implements and verifies DFT/DFD techniques for low-power, multi-voltage ASIC designs, including test pattern generation, coverage analysis, and simulation debug.
What you'll do
- Deploy DFT methodologies to reduce test cost, increase product quality, and improve yield learning.
- Generate DFT patterns and perform coverage analysis and debug.
- Run and debug gate-level simulations; work across pre- and post-silicon DFT.
What they ask for
- Hands-on experience with industry-standard DFT techniques such as scan and MBIST.
- Bachelor’s degree in Science, Engineering, or related field, or a Master’s or PhD in those fields, with the applicable experience listed.
- Knowledge of DFT implementation and verification.
Nice to have
- Understanding of core-based test methodology, scan isolation, fault models, JTAG, Scan Compression, ATPG, Fault Simulation, or at-speed testing.
- Experience with industry EDA ATPG and insertion tools.
Pay
USD $216,400.00 - $324,600.00 base salary
Tools
ASIC, DFT/DFD, scan, MBIST, JTAG, Scan Compression, ATPG, Fault Simulation
Model-written summary · the original posting is authoritative