Drimva

Qualcomm

EM Design Engineer

$148K–$222K

Santa Clara, California · On-site · Full-time · Posted Sep 17, 2026

Experience
Bachelor’s route: 3+ years designing RF/Analog circuits for wireless products and 2+ years of ASIC design, verification, or related work experience. Master’s route: 2+ years of ASIC design, verification, or related work experience. PhD route: no years specified. Separately, 2+ years using two or more of CADENCE, Virtuoso, ADS.
Education
Bachelor’s degree in Electrical Engineering; OR master’s degree in Electrical Engineering or related field; OR PhD in Electrical Engineering or related field.

About the job

Designs and models RF passive components and optimizes their performance, isolation, and integration in RF integrated circuits and multichip carriers.

What you'll do

  • Design and develop RF passive components for RFICs in 6nm and 14ff CMOS and SOI technologies, delivering compact models and DRC-clean physical designs.
  • Work with circuit designers to optimize component size and performance, and analyze and reduce on-chip and chip-to-package coupling.
  • Optimize multichip carriers for RF systems, focusing on loss and isolation.

What they ask for

  • Bachelor’s degree in Electrical Engineering with 3+ years designing RF/Analog circuits for wireless products and 2+ years of ASIC design, verification, or related work experience; OR a master’s degree in Electrical Engineering or related field and 2+ years of such work experience; OR a PhD in Electrical Engineering or related field.
  • 2+ years of academic or professional experience using two or more of CADENCE, Virtuoso, ADS.

Nice to have

  • Experience designing and simulating RF passive components, such as inductors, transformers, MOM capacitors, and passive filters.
  • Experience with EM simulation tools and techniques, compact RLCK model extraction, circuit design and layout, and predicting electric and magnetic coupling.

Pay

$147,900.00 - $221,900.00 USD (pay range; salary/base pay)

Tools

CMOS, SOI, MoM EM solvers, HFSS, EMX, Cadence, Agilent ADS, Virtuoso

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 5, 2026 (UTC)