GSoC Design Verification Engineer

What you'll do

• Develop verification plans, environments, tests, assertions, and coverage models for SoC, subsystem, and IP-level designs; debug issues and drive coverage closure.
• Collaborate with architecture, design, software, and verification teams to incorporate requirements early and support first-silicon success.
• Build AI-agent workflows, RAG pipelines, and tool integrations that automate engineering tasks and improve verification processes.

What they ask for

• Bachelor's or master's degree in electrical engineering, Computer Engineering, Computer Science, or a related field; minimum qualification also states a bachelor's degree in Science, Engineering, or a related field.
• Strong knowledge of System Verilog, UVM, C, SVA, coverage-driven verification, and system-level use-case verification.
• Experience developing verification environments from architecture/specification through signoff and debugging complex SoC-level issues.
• Proficiency in Python or scripting languages for automation; strong computer architecture and digital design fundamentals.

Nice to have

• Full-chip or subsystem verification, or experience in one or more listed areas such as CPU, cache coherency, memory systems, protocols, accelerators, security, or power/performance verification.
• Portable Stimulus, formal verification, emulation, power-aware verification, machine learning/Generative AI, or LLM knowledge.

Pay

$101,400.00 - $152,200.00 USD base salary

Tools

System Verilog, UVM, C, SVA, Python, ACE, CHI, CXL

AI focus

Develop AI agents, agent workflows, engineering-tool integrations, and RAG pipelines for verification and other engineering tasks; contribute to AI-assisted verification and measure productivity improvements.