High-Speed Analog & Mixed-Signal PHY Design Engineer

What you'll do

• Contribute to PHY architecture and transistor-level circuit design, and participate in design reviews.
• Work with layout teams to oversee block-level layouts.
• Run simulations and analyses, document results, and use them to improve and verify designs.

What they ask for

• Bachelor's in Electrical Engineering plus 2+ years of analog or mixed-signal IC design in nanometer planar CMOS or FinFET and 2+ years of ASIC design, verification, or related work; OR a master's in Electrical Engineering or related field and 2+ years of ASIC design, verification, or related work; OR a PhD in Electrical Engineering or related field.
• 2+ years using one or more design tools, such as CADENCE, SPICE, MATLAB, and/or Verilog/VHDL.

Nice to have

• PhD in Electrical Engineering or related field.
• 2+ years in analog/mixed-signal integrated CMOS circuit design in an area such as VCO, PLL, DLL, audio, ADC, DAC, DDR PHY, or high-speed SERDES design; >32Gbps transceiver or clocking design experience is highly desired.

Pay

$121,800.00 - $182,600.00 USD base salary

Tools

CMOS, FinFET, CADENCE, SPICE, MATLAB, Verilog/VHDL, VCO, PLL