Qualcomm
HW SOC/ASIC Physical Design Engineer, Senior/Staff (US Citizenship Required)
$122K–$183K
San Diego, California · On-site · Staff · Full-time · Posted Oct 26, 2026
- Experience
- 3+ years in physical design, focused on clock-tree design and implementation. Minimum education/experience alternatives: Bachelor’s plus 2+ years related ASIC experience; Master’s plus 1+ year related ASIC experience; or PhD.
- Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field; the minimum qualifications also list a PhD in Science, Engineering, or related field.
- Visa sponsorship
- Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
About the job
Executes ASIC physical design and signoff, focusing on clock-tree implementation, timing closure, physical verification, and power, performance, and area optimization through tapeout.
What you'll do
- Perform floorplanning, placement, clock-tree synthesis, routing, timing closure, and physical verification for block-level and full-chip designs.
- Develop and maintain automation, timing constraints, and verification flows; debug design issues and coordinate signoff with cross-functional teams, foundries, and EDA vendors.
- Optimize clocking and power architecture, support ECOs and tapeout preparation, and deliver clean, fully verified GDSII.
What they ask for
- Bachelor’s degree in Science, Engineering, or related field and 2+ years of related ASIC experience; OR Master’s degree in Science, Engineering, or related field and 1+ year of related ASIC experience; OR PhD in Science, Engineering, or related field.
- 3+ years of physical design experience, focused on clock-tree design and implementation.
- Proficiency with EDA tools for CTS, STA, and physical verification; scripting skills in TCL, Python, or Perl.
- Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
Nice to have
- Experience with advanced nodes (7nm, 5nm, 3nm) and FinFET technologies.
- Custom clock-tree architectures, EM/IR analysis, thermal-aware clocking, high-speed interface clocking, or package-level clock planning.
Pay
USD $121,800.00 - $182,600.00 (pay range; salary)
Tools
Innovus, ICC2, PrimeTime, Cadence Tempus, Calibre, Pegasus, ICV, TCL
Model-written summary · the original posting is authoritative