Qualcomm
Implementation Timing / STA Design Engineer
$146K–$218K
San Diego, California · On-site · Full-time · Posted Oct 27, 2026
- Experience
- Bachelor's: 4+ years; Master's: 3+ years; PhD: 2+ years of ASIC design, verification, validation, integration, or related work experience. The posting also says candidates should have at least 2 years of experience.
- Education
- Bachelor's, Master's, or PhD degree in Science, Engineering, or related field.
About the job
Develop and sign off timing constraints and static timing analysis for premium-tier SoCs, collaborating with RTL and physical design teams to achieve timing closure.
What you'll do
- Develop power-aware synthesis constraints and perform signoff static timing analysis across modes and corners.
- Collaborate with RTL and physical design teams to identify timing requirements and bottlenecks; generate, review, and validate clock-domain crossing and design constraints.
- Integrate HM constraints into SoC and analyze timing correlation, path pessimism, and margins.
What they ask for
- Proficiency with Primetime and Fishtail/TCM.
- Bachelor's degree in Science, Engineering, or related field, or a higher degree as specified in the education alternatives.
Nice to have
- Scripting skills in Tcl, Perl, or Python.
Pay
$145,600.00 - $218,400.00 USD base salary
Tools
Primetime, Fishtail/TCM, Tcl, Perl, Python
AI focus
The role supports SoCs across mobile, AI, and automotive sectors; no specific AI development work is stated.
Model-written summary · the original posting is authoritative