Qualcomm
Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer
$146K–$218K
San Diego, California · On-site · Full-time · Posted Oct 27, 2026
- Experience
- 5+ years ASIC design/RTL/front-end digital design and 3+ years hardware architecture. Minimum qualifications also state alternatives: bachelor's plus 4+ years, master's plus 3+ years, or PhD plus 2+ years in ASIC design, verification, validation, integration, or related work.
- Education
- Required: Master's in Computer Engineering and/or Electrical Engineering. Minimum qualifications also list a bachelor's, master's, or PhD in Science, Engineering, or a related field, with the stated experience alternatives.
About the job
Designs and deploys next-generation high-speed HBM/LPDDR/DDR memory-controller ASICs, from architecture and RTL through timing closure and chip integration.
What you'll do
- Develop architecture and design specifications, define microarchitecture, and implement RTL for high-speed memory systems.
- Debug designs and support verification, chip integration, synthesis, timing closure, physical design, gate-level simulation, and power analysis.
- Improve design methodology to increase productivity and quality.
What they ask for
- 5+ years of ASIC design, RTL coding, and front-end digital design experience.
- 3+ years of hardware architecture experience.
- Experience in high-speed digital design.
- Master's degree in Computer Engineering and/or Electrical Engineering is listed as required.
Nice to have
- Exposure to RTL design verification flows.
- Experience with LPDDR or HBM, cache controllers, NoC architectures, SRAM/L3 cache, x86 or ARM architectures, or memory transaction ordering.
Pay
$145,600.00 - $218,400.00 (base salary)
Tools
HBM, LPDDR, DDR, RTL, NoC, SRAM, L3 cache, x86 or ARM
Model-written summary · the original posting is authoritative