Qualcomm
Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
$146K–$218K
San Diego, California · On-site · Full-time · Posted Oct 27, 2026
- Experience
- 5+ years in ASIC design, RTL coding, and front-end digital design; 3+ years in Hardware Architecture. Minimum qualifications also state: Bachelor's plus 4+ years, Master's plus 3+ years, or PhD plus 2+ years of related work experience.
- Education
- Required: Bachelor's degree in Computer Engineering and/or Electrical Engineering. The posting also lists a Bachelor's, Master's, or PhD in Science, Engineering, or a related field under minimum qualifications.
About the job
Designs and delivers high-speed memory subsystem ASICs, from architecture and RTL through integration, timing closure, and power analysis.
What you'll do
- Develop architecture, micro-architecture, specifications, and RTL for high-speed memory subsystems.
- Debug designs and support integration; collaborate with verification engineers to deliver quality designs.
- Perform synthesis, timing closure, physical-design support, gate-level simulations, and power analysis.
What they ask for
- 5+ years of ASIC design, RTL coding, and front-end digital design experience.
- 3+ years of Hardware Architecture experience.
- Bachelor's degree in Science, Engineering, or related field, or the stated master's/PhD experience alternatives.
- Required education is a Bachelor's degree in Computer Engineering and/or Electrical Engineering.
Nice to have
- Exposure to RTL Design Verification flows.
- Master's degree in Computer Engineering and/or Electrical Engineering.
Pay
$145,600.00 - $218,400.00 USD base salary
Tools
HBM, LPDDR, DDR, RTL, NoC, SRAM, L3 cache, x86 or ARM
Model-written summary · the original posting is authoritative