Qualcomm
Next Gen, High-Speed, Memory and Cache Controller Design Engineer
$101K–$152K
San Diego, California · On-site · Full-time · Posted Oct 7, 2026
- Experience
- Welcomes recent graduates and early-career professionals with 3+ years of experience.
- Education
- Required: Master's in Computer Engineering and/or Electrical Engineering. The posting also lists a Bachelor's or Master's degree in Science, Engineering, or a related field.
About the job
Designs and deploys high-speed memory and cache controller logic for Qualcomm products, from architecture and RTL through implementation, timing closure, and debugging.
What you'll do
- Develop architecture, specifications, and micro-architecture for memory-controller logic; implement and deliver RTL.
- Support verification and chip integration, debug designs, and perform synthesis, timing closure, physical-design support, gate-level simulations, and power analysis.
- Improve design methodology to increase productivity and quality.
What they ask for
- Experience with LPDDR memory and cache controllers and NoC-based architectures, especially interfaces to CPU, DSP, and multimedia processors.
- Experience with x86 or ARM CPU/bus architectures.
- Knowledge of memory-transaction ordering and methods for enforcing ordering to conform to ISA specifications.
- Master's degree in Computer Engineering and/or Electrical Engineering.
Nice to have
- Exposure to HBM memory designs.
- Experience with on-chip tightly coupled SRAM and L3 cache controller architecture/design.
Pay
$101,400.00 - $152,200.00 USD (pay range; base salary or total pay not specified)
Tools
HBM, LPDDR, DDR, NoC, SRAM, L3 cache, x86, ARM
Model-written summary · the original posting is authoritative