Qualcomm
Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer
$146K–$218K
San Diego, California · On-site · Full-time · Posted Sep 17, 2026
- Experience
- 3+ years stated by the team; minimum qualifications specify 4+ years with a bachelor’s degree, 3+ with a master’s, or 2+ with a PhD.
- Education
- Bachelor’s, master’s, or PhD in Science, Engineering, or a related field. The posting separately specifies qualifying degrees in Computer Engineering, Computer Science, Electrical Engineering, or a related field, with GPA > 3.5 for bachelor’s and master’s degrees.
About the job
Designs and validates RTL for SoC interconnects, caches, and memory subsystems, optimizing performance, power, and silicon cost across Qualcomm platforms.
What you'll do
- Develop microarchitecture, specifications, and RTL for SoC interconnect, cache, and memory-subsystem designs.
- Perform design verification, debugging, and validation throughout project cycles; troubleshoot silicon issues.
- Optimize hardware for performance, power, cost, and clock speed; assess feasibility of complex algorithms and requirements.
What they ask for
- Experience or coursework in Verilog/SystemVerilog design, Synopsys synthesis, low-power design, test-plan development, and coverage-based design verification.
- Bachelor’s degree in Science, Engineering, or related field and 4+ years of relevant work experience; OR master’s degree and 3+ years; OR PhD and 2+ years.
- Strong communication skills and ability to work as a team player.
Nice to have
- Experience or coursework in Computer Architecture, Computer Arithmetic, C/C++/Python, or low-power design.
- Experience designing RTL for CPU or cache-controller blocks in ASIC; prior ASIC Design and DV experience is a plus.
Pay
$145,600.00 - $218,400.00 (USD, base salary)
Tools
Verilog, SystemVerilog, Synopsys, C/C++, Python, ASIC
Model-written summary · the original posting is authoritative