Qualcomm
Next-Gen System Cache ASIC Digital Design Engineer
$122K–$183K
San Diego, California · On-site · Full-time · Posted Oct 7, 2026
- Experience
- The team welcomes recent graduates and early-career professionals with 3+ years of experience. Minimum qualifications also specify a bachelor's degree and 2+ years of related ASIC experience, or a master's degree and 1+ year, or a PhD.
- Education
- Bachelor's or master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field, each with GPA > 3.5; or PhD in those fields.
About the job
Designs and validates RTL for SoC interconnects, caches, and memory subsystems, optimizing hardware for performance, power, and cost.
What you'll do
- Develop microarchitecture, specifications, and RTL for interconnect, cache, and memory subsystem designs.
- Perform verification, debugging, and validation throughout project cycles; troubleshoot silicon issues.
- Optimize hardware performance, power, clock speed, and silicon cost; evaluate feasibility of complex requirements.
What they ask for
- Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with GPA > 3.5; or master's degree in those fields with GPA > 3.5; or PhD in those fields.
- Experience or coursework in Verilog/SystemVerilog design, Synopsys synthesis, low-power design, test plan development, or coverage-based design verification.
- Good communication skills and desire to work as a team player.
Nice to have
- Experience or coursework in Computer Architecture, Computer Arithmetic, low-power design, or C/C++/Python programming.
- Experience designing ASIC RTL for CPU or cache controller blocks; prior ASIC design and DV experience is a plus.
Pay
$121,800.00 - $182,600.00 USD base salary
Tools
Verilog/SystemVerilog, Synopsys, C/C++, Python
Model-written summary · the original posting is authoritative