Qualcomm
NoC Interconnect Design Engineer and Architect
$134K–$202K
Santa Clara, California · On-site · Full-time · Posted Oct 30, 2026
- Experience
- Bachelor's: 2+ years; master's: 1+ year; PhD: no experience specified. Preferred: 3+ years ASIC experience and 2+ years in the listed tool, programming, or verification areas.
- Education
- Bachelor's or master's degree in Science, Engineering, or related field, or PhD in those fields.
About the job
Defines and develops ASIC IP and SoC architectures, designs, and implementations, collaborating across teams to meet system requirements.
What you'll do
- Define, design, optimize, verify, validate, implement, and document ASIC IP and SoC development.
- Create architectures, circuit specifications, logic designs, and system simulations from system-level requirements.
- Evaluate design flows and use tools such as RTL to GDS Flow and Virtuoso for block, SoC, or IC package design.
What they ask for
- Bachelor's degree in Science, Engineering, or related field and 2+ years of relevant ASIC experience; or a master's degree in those fields and 1+ year; or a PhD in those fields.
- Experience in ASIC design, verification, validation, integration, or related work, as specified in the applicable education path.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 3+ years of relevant ASIC experience; 2+ years with architecture and design tools, scripting tools and programming languages, or design verification methods.
Pay
$134,500.00 - $201,700.00 USD base salary
Tools
RTL to GDS Flow, Virtuoso
Model-written summary · the original posting is authoritative