Qualcomm
NoC Interconnect Design Engineer and Architect
$122K–$183K
San Diego, California · On-site · Full-time · Posted Oct 30, 2026
- Experience
- Bachelor's degree: 2+ years of ASIC design, verification, validation, integration, or related work experience; or master's degree: 1+ year of such experience; or PhD (no experience stated).
- Education
- Bachelor's, master's, or PhD degree in Science, Engineering, or a related field.
About the job
Designs and architects NoC interconnects for SoCs, from bus micro-architecture specifications and performance analysis through RTL delivery and deployment support.
What you'll do
- Specify bus-component micro-architecture, analyze performance results, deliver RTL, and run tool flows.
- Evaluate IPs, deploy protocols, and define system-wide guidelines for IP interoperability in the SoC.
- Support verification, silicon validation, and software teams during interconnect deployment.
What they ask for
- Knowledge of bus protocols such as AHB, AXI, and CHI, and network on chip.
- Strong knowledge of architecture tradeoff analysis and ASIC flows, including synthesis, STA, and Lint, as well as power tools.
- RTL design, FPGA, and post-silicon debugging skills; ability to define bus-component micro-architecture considering performance, power, and area.
- Excellent communication skills and ability to adapt to changes.
Nice to have
- Familiarity with CPU architecture.
Pay
$121,800.00 - $182,600.00 (base salary)
Tools
AHB, AXI, CHI, ASIC, RTL, FPGA, STA, Lint
Model-written summary · the original posting is authoritative