Qualcomm
Package Design Engineer - Staff
$160K–$240K
San Diego, California · On-site · Staff · Full-time · Posted Sep 17, 2026
- Experience
- Preferred qualifications specify 5+ years of experience.
- Education
- Preferred: Master's degree in electrical engineering, mechanical engineering, material science, or related fields.
About the job
Leads package selection and physical design for SoC packages and modules, optimizing layout, verification, and mechanical, electrical, and thermal performance through tape-out.
What you'll do
- Drive package selection, structure, configuration, layout, optimization, design verification, and tape-out.
- Coordinate with cross-functional teams to optimize package pinout, SI/PI, chip floorplan, bump placement, and package size.
- Develop verification and automation strategies, improve design flows, and evaluate CAD tools with vendors and developers.
What they ask for
- Proficiency in Cadence APD & SiP and/or Siemens Xpedition Package Designer (xPD).
- Familiarity with Constraint Manager for package-design DFM and electrical rules.
- Basic signal-integrity knowledge for high-speed IO interfaces, transmission lines, and electromagnetic field theory.
- Knowledge of IC packaging structures and chip-package and package-board interactions.
Nice to have
- Experience with in-line DRC checking, DFM verification, and Electrical Rule Checking (ERC).
- Knowledge of electronic packaging processes and typical failure modes.
Pay
$160,200.00 - $240,200.00 USD base salary
Tools
Cadence APD & SiP, Siemens Xpedition Package Designer (xPD), Cadence Allegro, XtractIM, PowerSI, HFSS, Q3D, Calibre
Model-written summary · the original posting is authoritative