Drimva

Qualcomm

Performance Modeling Engineer Processor, AI Accelerator, and SoC Architecture- Sr.Staff

$192K–$288K

Austin, Texas · On-site · Staff · Full-time · Posted Oct 1, 2026

Experience
10+ years of industry experience in computer architecture, microarchitecture, or performance modeling; 2+ years of high-performance microprocessor design experience. Minimum qualifications also list 6+ years with a bachelor's degree, 5+ with a master's, or 4+ with a PhD in a related field.
Education
BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field.

About the job

Develops performance models and analyzes architectural tradeoffs for next-generation processors, AI accelerators, and SoC platforms to guide design decisions from concept through silicon.

What you'll do

  • Develop and maintain transaction-level and analytical models of processors, memory systems, interconnects, and accelerators; analyze workloads and system bottlenecks.
  • Evaluate architectural tradeoffs and conduct performance studies of multicore, cache-coherent systems.
  • Correlate models with RTL simulations, emulation, and silicon data, and present architectural recommendations.

What they ask for

  • BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
  • 10+ years of industry experience in computer architecture, microarchitecture, or performance modeling.
  • 2+ years of experience with high-performance microprocessor design.
  • Experience developing TLM/SystemC models, analytical performance models, and architectural simulators; strong software skills in C++, Python, or equivalent languages.

Nice to have

  • Experience modeling AI accelerators, CPUs, GPUs, or heterogeneous compute architectures.
  • Experience correlating pre-silicon models with silicon measurements and performance counters.

Pay

$191,800.00 - $287,800.00 USD base salary

Tools

TLM/SystemC, C++, Python, ARM CHI, ACE, MESI/MOESI

AI focus

Models and evaluates AI accelerator architecture and performance.

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 4, 2026 (UTC)