Qualcomm
Physical Design Engineer
$146K–$218K
Austin, Texas · On-site · Full-time · Posted Oct 29, 2026
- Experience
- The posting states 2–10+ years of industry or relevant academic/project experience in Physical Design. Minimum qualifications also specify: Bachelor's degree plus 4+ years, Master's plus 3+ years, or PhD plus 2+ years in ASIC design, verification, validation, integration, or related work.
- Education
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Minimum qualifications also list a Bachelor's, Master's, or PhD in Science, Engineering, or a related field.
About the job
Executes end-to-end physical design for ASICs and SoCs, from synthesized netlist through implementation, timing closure, verification, and tape-out.
What you'll do
- Drive physical design flows, including floorplanning, power planning, placement, CTS, routing, timing optimization, and sign-off.
- Analyze and resolve timing, signal integrity, crosstalk, IR-drop, and design-rule issues; implement ECOs.
- Collaborate across design teams and develop automation tools and low-power implementation methodologies.
What they ask for
- Bachelor's, Master's, or PhD in a related technical field, with the experience alternatives stated below.
- Physical Design or related ASIC experience; the posting also specifies relevant academic/project experience.
- Perl/Tcl and Python skills are needed.
Nice to have
- Experience with ASIC/SoC implementation, place-and-route, timing analysis, physical/formal verification, or sign-off.
- Experience with low-power design, CTS, signal integrity/MMMC, DFT-aware implementation, and scripting.
Pay
$145,600.00 - $218,400.00 (USD, base salary)
Tools
Cadence Innovus, Synopsys Fusion Compiler, Synopsys PrimeTime SI, Python, Perl, TCL, Shell scripting, C/C++
Model-written summary · the original posting is authoritative