Drimva

Qualcomm

Physical Design Engineer - DSP Team

$174K–$262K

Austin, Texas · On-site · Full-time · Posted Sep 17, 2026

Experience
12+ years in ASIC physical design, synthesis, or related work experience. Minimum qualifications also state 6+ years with a bachelor's degree, 5+ with a master's, or 4+ with a PhD in a related field. Preferred: 15+ years CPU/GPU design; 10+ years with architecture and design tools; 10+ years with scripting tools and programming languages.
Education
Bachelor's degree in Science, Engineering, or related field; alternatively, a Master's degree or PhD in Science, Engineering, or related field under the stated minimum-qualification experience alternatives.

About the job

Develop and optimize ASIC physical-design flows and complex DSP blocks for power, performance, and area (PPA), from synthesis through physical-design convergence.

What you'll do

  • Update implementation flows and develop semi-custom design techniques to improve PPA, utilization, performance, and power efficiency.
  • Use and enhance design methodologies and scripting to achieve PPA goals; collaborate with physical-design and logic teams.
  • Execute architecture and design tools and advanced power checks on complex blocks, recommending solutions when specifications are not met.

What they ask for

  • Bachelor's degree in Science, Engineering, or a related field; alternatively, a Master's degree with 5+ years or a PhD with 4+ years of related ASIC experience.
  • 12+ years of ASIC physical design, synthesis, or related work experience.
  • Strong proficiency in P&R, timing analysis, and CAD tools.
  • Very good understanding of logic optimization, clock structures, and power optimization.

Nice to have

  • Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering.
  • 15+ years of CPU or GPU design experience; 10+ years with architecture and design tools or scripting tools and programming languages.

Pay

$174,400.00 - $261,600.00 USD base salary

Tools

Fusion Compiler, Synopsys FC/DC, ICC2, Cadence Genus, Innovus

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 5, 2026 (UTC)