Qualcomm
Physical Design Engineer
$174K–$262K
San Diego, California · On-site · Full-time · Posted Oct 19, 2026
- Experience
- 10+ years of industry experience or relevant academic/project experience in Physical Design. Minimum qualifications also list alternatives: Bachelor's degree and 6+ years, Master's degree and 5+ years, or PhD and 4+ years of related ASIC experience.
- Education
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Minimum qualifications also list a Bachelor's, Master's, or PhD in Science, Engineering, or a related field.
About the job
Executes ASIC and SoC physical design from synthesized netlist through tape-out, including implementation, optimization, verification, and sign-off.
What you'll do
- Drive physical design flow stages, including floorplanning, power planning, placement, CTS, routing, timing closure, and sign-off.
- Analyze and resolve timing, signal integrity, crosstalk, IR-drop, and physical design rule issues; perform verification and ECOs.
- Collaborate across design teams and develop low-power methodologies, place-and-route solutions, and automation tools.
What they ask for
- 10+ years of industry experience or relevant academic/project experience in Physical Design.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- Perl/Tcl and Python skills are needed.
- Strong problem solving and ASIC development/debugging skills.
Nice to have
- Experience with ASIC/SoC physical design, place and route, timing analysis, physical verification, or sign-off methodologies.
- Experience with low-power implementation, CTS, signal integrity, MMMC flows, DFT-aware implementation, and automation.
Pay
$174,400.00 - $261,600.00 USD base salary
Tools
Cadence Innovus, Synopsys Fusion Compiler, Synopsys PrimeTime SI, Python, Perl, TCL, Shell scripting, C/C++
Model-written summary · the original posting is authoritative