Qualcomm
Physical Design Engineer
$160K–$239K
Santa Clara, California · On-site · Full-time · Posted Oct 29, 2026
- Experience
- The posting states 2–10+ years of industry or relevant academic/project experience in Physical Design. Minimum qualifications also specify a Bachelor's degree and 4+ years, a Master's and 3+ years, or a PhD and 2+ years of related ASIC experience.
- Education
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Minimum qualifications also list a PhD in Science, Engineering, or a related field.
About the job
Executes end-to-end physical design for ASICs and SoCs, from synthesized netlist through tape-out and sign-off.
What you'll do
- Perform floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, and physical verification.
- Analyze and resolve timing, signal integrity, crosstalk, IR-drop, and design-rule issues; implement ECOs and support sign-off.
- Collaborate across design teams and develop low-power methodologies, place-and-route solutions, and automation tools.
What they ask for
- Bachelor's, Master's, or PhD in Science, Engineering, or a related field, with the stated experience alternatives.
- Physical Design experience, including relevant industry or academic/project experience.
- Perl/Tcl and Python skills are needed.
Nice to have
- Experience with ASIC/SoC physical design, place-and-route, timing analysis, verification, or sign-off.
- Experience with low-power implementation, CTS, signal integrity, MMMC flows, or scripting and Linux/Unix environments.
Pay
$159,600.00 - $239,400.00 USD base salary
Tools
Cadence Innovus, Synopsys Fusion Compiler, Synopsys PrimeTime SI, Python, Perl, TCL, Shell scripting, C/C++
AI focus
The role may contribute to projects spanning AI; no specific AI-focused work is described.
Model-written summary · the original posting is authoritative