Qualcomm
Physical Design Engineer, Staff
$146K–$218K
Austin, Texas · On-site · Staff · Full-time · Posted Sep 24, 2026
- Experience
- Bachelor’s: 4+ years; master’s: 3+ years; PhD: 2+ years in ASIC design, verification, validation, integration, or related work. Preferred: 6+ years in these areas; 2+ years with architecture and design tools, scripting and programming languages, and design verification methods; 1+ year interacting with senior leadership.
- Education
- Bachelor's, master's, or PhD in Science, Engineering, or a related field.
About the job
Designs and implements ASIC IP, blocks, and SoCs, optimizing their performance, quality, and power while coordinating implementation across teams.
What you'll do
- Define, design, optimize, verify, implement, and document ASIC IP, blocks, and SoCs.
- Evaluate design flows, including synthesis, place and route, timing, power, and verification.
- Coordinate implementation strategies with cross-functional teams and document project work.
What they ask for
- Bachelor’s degree in Science, Engineering, or a related field and 4+ years of relevant experience; or a master’s degree and 3+ years; or a PhD and 2+ years.
- Experience in ASIC design, verification, validation, integration, or related work.
Nice to have
- Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- Experience with architecture and design tools, scripting and programming languages, design verification methods, or senior-leadership interaction.
Pay
$145,600.00 - $218,400.00 USD base salary
Tools
RTL to GDS Flow, Virtuoso
Model-written summary · the original posting is authoritative