Qualcomm
Physical Design Engineer- Staff to Sr. Staff
$174K–$262K
Austin, Texas · On-site · Senior Staff · Full-time · Posted Sep 29, 2026
- Experience
- 10+ years of industry experience in ASIC/SoC physical design. Minimum qualifications also list Bachelor's degree and 6+ years, Master's degree and 5+ years, or PhD and 4+ years in ASIC design, verification, validation, integration, or related work experience.
- Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. Minimum qualifications also list a Bachelor's, Master's, or PhD in Science, Engineering, or a related field.
About the job
Leads clock physical design for advanced NSP ASIC/SoC designs, from architecture and implementation through optimization, timing closure, and tapeout signoff.
What you'll do
- Architect, implement, optimize, and sign off clock distribution structures, including H-trees, meshes, spines, hierarchical distribution, and low-power clocking.
- Analyze clock timing, power, signal integrity, variation, and reliability using SPICE, PrimeTime, and related tools; drive clock convergence and tapeout readiness.
- Develop clock implementation methods and automation, support ECOs, and guide engineers while coordinating across physical design, timing, PLL, power, CAD, RTL, and architecture teams.
What they ask for
- 10+ years of industry experience in ASIC/SoC physical design, including hands-on high-performance clock implementation and timing closure.
- Proven experience taking complex ASIC/SoC designs through physical design convergence and successful tapeout.
- Hands-on SPICE simulation and experience with industry-standard physical design and signoff tools, including Synopsys Fusion Compiler / ICC2 and/or Cadence Innovus, Synopsys PrimeTime, extraction, and physical verification flows.
- Proficiency in TCL, Python, Perl, and Linux/Unix environments.
Nice to have
- Experience developing custom clock methodologies for high-frequency designs and working with advanced technology nodes.
- Familiarity with Infinisim or PrimeClock; experience correlating SPICE, STA, extraction, and physical implementation results.
Pay
$174,400.00 - $261,600.00 USD base salary
Tools
SPICE, Synopsys Fusion Compiler / ICC2, Cadence Innovus, Synopsys PrimeTime, TCL, Python, Perl, Linux/Unix
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