Drimva

Qualcomm

Power Management IC Design

$134K–$202K

Santa Clara, California · On-site · Full-time · Posted Sep 17, 2026

Experience
Bachelor's: 4+ years of relevant IC Design experience; Master's: 2+ years of relevant IC Design experience; PhD: no experience duration specified. Also requires 2+ years of academic and/or work experience using listed tools. Preferred: 3+ years of relevant design experience with a Master's Degree or PhD.
Education
Bachelor's degree in Electrical Engineering; OR Master's degree in Electrical Engineering or related field; OR PhD in Electrical Engineering or related field.

About the job

Designs, verifies, and documents mixed-signal power management ICs, including controller circuitry and high-current power stage interfaces, and supports layout, silicon bring-up, characterization, and debug.

What you'll do

  • Define architectures and design and verify IC blocks and subsystems; guide layout and conduct physical and reliability verification.
  • Analyze simulation and silicon results, ensure performance across PVT and operating conditions, and drive corrective design actions.
  • Collaborate with validation, test, and product engineering on silicon bring-up and qualification; document designs and provide technical guidance.

What they ask for

  • Bachelor's degree in Electrical Engineering and 4+ years of relevant IC Design experience; OR Master's degree in Electrical Engineering or related field and 2+ years of relevant IC Design experience; OR PhD in Electrical Engineering or related field.
  • 2+ years of academic and/or work experience using CADENCE, SPICE, MATLAB, and/or Verilog/VHDL.

Nice to have

  • 3+ years of analog, mixed-signal, or Power Management integrated circuit design experience with a Master's Degree or PhD in Electrical Engineering.
  • Experience in one or more listed areas, including Power Electronics, Control Theory, Multiphase Buck Controllers, or Mixed-Signal Verification Techniques.

Pay

$134,500.00 - $201,700.00 (base salary)

Tools

Cadence ADE, Spectre, MathWorks MATLAB, Verilog/Verilog-AMS, SystemVerilog, Simplis, CADENCE, SPICE

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 5, 2026 (UTC)