Qualcomm
Principal CPU Physical Design Engineer (San Diego, CA)
$217K–$325K
San Diego, California · On-site · Principal · Full-time · Posted Sep 22, 2026
- Experience
- 10+ years in ASIC/SoC Physical Design; minimum qualifications also specify 8+ years with a bachelor’s degree, 7+ with a master’s, or 6+ with a PhD.
- Education
- Bachelor’s, master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Leads physical implementation and optimization of CPU designs from RTL to GDS, improving performance, power, area, and design quality while collaborating across engineering teams.
What you'll do
- Own CPU implementation from RTL to GDS, driving PPA convergence and design quality.
- Optimize timing, power, and area; resolve timing closure, congestion, variability, EM/IR, and power-integrity issues.
- Develop methodologies and automation, collaborate with EDA and CAD teams, and mentor engineers.
What they ask for
- Strong experience with full RTL-to-GDSII implementation, including synthesis, place & route, STA, and signoff.
- Experience in timing closure and power optimization.
- Scripting skills in TCL, Python, or similar.
- Bachelor’s degree in a specified related field and 8+ years of related work experience; or master’s and 7+ years; or PhD and 6+ years.
Nice to have
- Experience with CPU cores or other high-performance designs and advanced nodes (7nm, 5nm, 3nm or below).
- Hands-on Synopsys/Cadence tools, design-methodology development, and strong data-driven analytical skills.
Pay
$216,600.00 - $325,000.00 USD (base salary)
Tools
RTL, GDSII, TCL, Python, Synopsys, Cadence
Model-written summary · the original posting is authoritative