Drimva

Qualcomm

RF Package Design Engineer, Senior Staff

$192K–$288K

San Diego, California · On-site · Senior Staff · Full-time · Posted Oct 13, 2026

Experience
10+ years of RF Package/PCB design experience. Also lists 6+ years with a bachelor's degree, 5+ years with a master's degree, or 4+ years with a PhD in System/Package Design/Technology Engineering or related work. Preferred: Ph.D. with 10+ years or master's degree with 15+ years.
Education
Master's degree in Science, Engineering, or related field. Also lists bachelor's, master's, or PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field.

About the job

Leads RF package design and electrical characterization for 6G products, advancing packaging roadmaps, technical capabilities, and engineering teams.

What you'll do

  • Coordinate package design trade-offs with package designers and RF-IC block owners; establish extraction and simulation methodologies and guide troubleshooting.
  • Advance RF packaging technology, improve and automate design and analysis flows, and create technical documentation and presentations.
  • Recruit, lead, train, and mentor engineers; define packaging roadmaps and resource needs.

What they ask for

  • 10+ years of RF Package/PCB design experience.
  • Solid understanding and experience in electromagnetics, transmission line theory, and crosstalk.
  • Proficiency with field solvers such as Ansys HFSS, Q3D, and PSI, and simulation tools such as ADS and Hspice.
  • Good knowledge of design tools such as Cadence Allegro/APD/Sip or Mentor Xpedition.

Nice to have

  • Familiarity with Analog & RF-IC design; proficiency in MatLab.
  • Programming or scripting experience (c/c++, Perl, or Python); people management experience is a plus.

Pay

$191,800.00 - $287,800.00 USD base salary

Tools

Ansys Electronic Desk Suite, HFSS, 3D Layout, Q3D, SIWave, ADS, Hspice, Cadence Allegro/APD/Sip

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 5, 2026 (UTC)