Drimva

Qualcomm

Senior AI Performance Architect

$127K–$190K

San Diego, California +4 · On-site · Senior · Full-time · Posted Oct 28, 2026

Location
San Diego, California
Austin, Texas
Folsom, California
Raleigh, North Carolina
Santa Clara, California
Experience
3+ years in hardware engineering defining architecture of GPUs or accelerators used for AI training. The posting also lists minimum qualification alternatives: bachelor's degree plus 2+ years of relevant work experience; master's degree plus 1+ year; or a PhD.
Education
Master's degree in Computer Science, Engineering, Information Systems, or related field. Minimum qualifications also list bachelor's or master's degree in these fields, or a PhD.

About the job

Architects and evaluates AI accelerator hardware and systems to improve performance, power efficiency, and scalability for AI model training.

What you'll do

  • Determine how ML trends and customer requirements affect hardware and software architecture; analyze existing accelerator and GPU architectures.
  • Architect accelerator, memory, and scale-out/scale-up enhancements, including hardware/software co-design for AI training workloads.
  • Build performance models and pre-silicon predictions; assess performance, area, and power trade-offs.

What they ask for

  • At least 3 years of hardware engineering experience defining GPU or AI-training accelerator architecture.
  • In-depth knowledge of nVidia/AMD GPU capabilities and architectures.
  • Knowledge of LLM architectures and their hardware requirements.
  • Master's degree in Computer Science, Engineering, Information Systems, or a related field.

Nice to have

  • Knowledge of computer architecture, digital circuits, hardware simulators, communication protocols, NoC designs, and memory technologies.
  • Experience modeling hardware and workloads for performance and power estimates; high-level hardware modeling experience.

Pay

$126,700.00 - $190,100.00 USD base salary

Tools

GEMM, GEMV, NoC, SoC, C++, Python, DeepSpeed, FSDP

AI focus

AI accelerator architecture for training, including LLM hardware requirements, AI training systems, workload performance modeling, and hardware/software co-design.

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 5, 2026 (UTC)