Senior Leader, Signal and Power Integrity/Systems Architecture (High-Speed Interconnects) - Multiple locations

What you'll do

• Lead end-to-end architecture for 224G and 448G PAM4 interconnects across SerDes, packages, boards, connectors, cables, and rack-scale systems.
• Set system-level signal and power integrity strategy, including channel modeling, compliance, PDN design, and simulation-to-silicon correlation.
• Drive link technology optimization and productization with cross-functional teams, and guide future interconnect roadmaps.

What they ask for

• MS or PhD in Electrical Engineering, Computer Engineering, Physics, or a related discipline.
• 15+ years developing high-speed communication, networking, or datacenter infrastructure products.
• Demonstrated success productizing 112G and/or 224G PAM4 electrical communication systems.
• Deep expertise in high-speed SerDes, PAM4, SI/PI, package/PCB/interconnect design, channel modeling, and end-to-end electrical system architecture.

Nice to have

• Experience with 224G+ and 448G interconnects, CPC/NPC and copper flyover architectures, AECs, advanced package substrates, or next-generation PCB technologies.
• Familiarity with Ethernet, PCIe, UALink, NVLink, OIF CEI, IEEE 802.3, chiplets, UCIe, and heterogeneous integration.

Pay

$256,600.00 - $385,000.00 USD base salary

Tools

ADS, HFSS, CST, HSPICE, MATLAB, Python, Cadence Sigrity, PowerSI

AI focus

Develops high-speed interconnect technologies and electrical architectures for AI infrastructure and AI networking systems.