SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)

What you'll do

• Plan, document, review, and execute bare-metal validation for clock and power architectures across standalone and system-level scenarios.
• Develop C drivers and tests, and automate validation workflows using Python, Perl, and shell.
• Debug pre- and post-silicon issues, guide root-cause analysis, and support power-subsystem bring-up and production readiness.

What they ask for

• Bachelor’s degree in engineering or related field, or the stated alternative degree and experience combinations.
• 5+ years of relevant SoC validation or associated experience; the minimum qualifications also state 4+ years with a bachelor’s, 3+ with a master’s, or 2+ with a PhD.
• Prior work experience in clock/power validation.
• Proficiency in C and Python; experience with lab instruments and exposure to debug tools such as JTAG.

Nice to have

• Experience with cross-compilers, linkers, and makefiles; understanding of coherency and concurrency in modern SoCs.
• Knowledge of PMIC and rail-power validation, FPGA-based emulation, or RTL/HDLs such as Verilog/System Verilog.

Pay

$145,600.00 - $218,400.00 USD base salary

Tools

C, Python, Perl, shell, JTAG, ARM, Verilog, System Verilog

AI focus

Validates clock, power, reset, and power-management systems for AI accelerator platforms, including operation under AI training and inference workloads.