Qualcomm
SOC Design Verification Engineer
$122K–$183K
San Diego, California · On-site · Full-time · Posted Oct 6, 2026
- Experience
- Minimum 2+ years of design verification experience; minimum qualifications also state bachelor’s plus 2+ years of ASIC design, verification, validation, integration, or related work experience, or master’s plus 1+ year, or PhD. Senior positions offered to candidates with proven expertise.
- Education
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, Computer Science, or related field. Minimum qualifications also allow a PhD in Science, Engineering, or related field.
About the job
Verifies Qualcomm data-center SoCs, developing scalable verification environments and driving coverage closure to support first-silicon success.
What you'll do
- Develop and execute verification plans, environments, tests, assertions, coverage models, and checkers for SoC, subsystem, and IP features.
- Debug verification and integration issues, collaborate with design teams, and drive coverage closure.
- Support emulation, methodology improvements, reusable components, automation, and AI-assisted verification flows.
What they ask for
- Strong knowledge of System Verilog, UVM, C, SVA, coverage-driven verification, and system-level use-case verification.
- Experience developing verification environments from architecture/specification through signoff.
- Strong understanding of computer architecture and digital design fundamentals; experience debugging complex SoC-level issues.
- Bachelor’s degree in a related field plus 2+ years of ASIC-related work experience; or master’s plus 1+ year; or PhD. A separate qualification also states a bachelor’s or master’s degree in a related field and 2+ years of design verification experience.
Nice to have
- Experience in areas such as CPU, memory, interconnect, AI/ML accelerator, security, RAS, or system performance/power verification; or with PSS, formal verification, emulation, or power-aware verification.
- Proficiency in Python or scripting languages; experience with AI-assisted verification workflows and test generation.
Pay
$121,800.00 - $182,600.00 USD base salary
Tools
System Verilog, UVM, C, SVA, Python, Portable Stimulus (PSS), Veloce/Palladium/ZeBu, DDR/HBM
AI focus
Contributes to AI-assisted verification flows; preferred experience includes AI-assisted verification workflows and test generation. The role verifies AI/ML accelerators.
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