SOC Design Verification Engineer – Data Center Solutions

What you'll do

• Develop verification plans and System Verilog/UVM-based or processor-based environments, tests, assertions, coverage models, and checkers.
• Debug SoC design and integration issues, drive functional and code coverage closure, and collaborate with design and architecture teams.
• Verify data center SoC features and contribute to emulation, reusable components, automation, methodology improvements, and AI-assisted verification flows.

What they ask for

• Strong knowledge of System Verilog, UVM, C, Assertion-Based Verification (SVA), Coverage-Driven Verification, and system-level use case verification.
• Experience developing verification environments from architecture/specification through signoff.
• Strong understanding of computer architecture and digital design fundamentals; experience debugging complex SoC-level issues.
• Bachelor’s degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience; OR master’s degree and 1+ year; OR PhD.

Nice to have

• Experience in CPU, cache coherency, memory, high-speed interfaces, AI/ML accelerator, security/RAS, performance, power, or post-silicon verification.
• Experience with Portable Stimulus (PSS), Formal Verification, emulation platforms, power-aware verification, Python or scripting, or AI-assisted verification.

Pay

$121,800.00 - $182,600.00 USD base salary

Tools

System Verilog, UVM, C, SVA, ACE, CHI, CXL, Python

AI focus

Contributes to AI-assisted verification flows and test generation, and verifies AI/ML accelerator functionality.