Qualcomm
SoC Infrastructure/NoC, Power & Performance Validation Engineer
$122K–$183K
San Diego, California +4 · On-site · Full-time · Posted Oct 16, 2026
- Location
- San Diego, California
Austin, Texas
Folsom, California
Hillsboro, Oregon
Santa Clara, California - Experience
- One of the stated alternatives: bachelor's degree and 5+ years of ASIC design, validation, verification, or related work; master's degree and 4+ years; or PhD and 3+ years. A second set of minimum qualifications states: bachelor's degree and 2+ years of ASIC design, verification, validation, integration, or related work; master's degree and 1+ year; or PhD.
- Education
- Bachelor's, master's, or PhD in Science, Engineering, or a related field.
About the job
Validates SoC infrastructure, NoC, power, and performance in pre-silicon emulation and post-silicon, including developing and analyzing tests for SoC bus architecture.
What you'll do
- Develop validation plans and test content for SoC bandwidth, interconnects, power, and performance.
- Analyze performance-power trade-offs and validate system features across low-power modes, clock and voltage scaling, and interrupt and debug architectures.
- Develop drivers and test content, and debug low-level software and hardware issues.
What they ask for
- Knowledge of SoC bandwidth, QoS, latency, throughput, interconnect architectures, and FIFO design.
- Experience with embedded systems and expertise in C, C++, Python, and assembly languages.
- Understanding of power in semiconductor design, CPU and DDR concepts, memory hierarchy, caches, and full-system concurrency.
- Experience with debug tools including JTAG and kernel debuggers.
Nice to have
- Experience leveraging Generative AI technologies to optimize workflows.
Pay
$121,800.00 - $182,600.00 (base salary)
Tools
NoCs, AXI, AHB, C, C++, Python, JTAG
AI focus
Experience leveraging Generative AI technologies for optimizing workflows.
Model-written summary · the original posting is authoritative