SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)

What you'll do

• Develop performance validation plans and analyze SoC bandwidth, QoS, latency, and throughput, accounting for power-performance trade-offs.
• Evaluate AI training and inference workloads and correlate pre-silicon models, emulation, and silicon performance measurements.
• Develop validation content and methodologies, and create performance dashboards, reports, and technical reviews.

What they ask for

• At least 7 years of experience in silicon validation or platform bring-up; the posting also lists ASIC experience alternatives of 4+ years with a bachelor's, 3+ with a master's, or 2+ with a PhD.
• Knowledge of interconnect architectures such as NoCs, AXI, and AHB, including transaction-stress programming; expertise in FIFO designs.
• Experience with embedded systems and C, C++, Python, and assembly; driver and test-content implementation.
• Experience debugging complex hardware/software issues and with performance counters, telemetry, power concepts, and system validation.

Nice to have

• Understanding of computer architecture, AI/ML accelerators, memory hierarchy, cache coherency, and on-chip interconnects.
• Knowledge of AI/ML workloads, tensor operations, matrix multiplication, transformer models, and large-scale inference systems; familiarity with system-level debug and silicon bring-up.

Pay

$145,600.00 - $218,400.00 USD base salary

Tools

NoCs, AXI, AHB, C, C++, Python, JTAG, MTE, MPAM

AI focus

Validates AI accelerator performance by evaluating inference and training workloads for throughput, latency, memory bandwidth, and power-performance efficiency.